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dual - channel isolators with integrated dc - to - dc converter s data sheet adum5210 / adum5211 / adum5212 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is g ranted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features iso power integrated, isolated dc - to - dc converter regulated 3. 15 v to 5 .25 v output up to 150 mw output power dual dc - to - 1 00 mbps (nrz) signal isolation channels soft start power supply 20- lead s sop package with 5 .3 mm creepage supports spi up to 1 5 mhz high temperature operation: 105c high common - mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition (pending) 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a (pending) vde certificate of conformity (pending) din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 560 v peak applications rs - 232 transceivers power supply start - up bias and gate drives isolated sensor interfaces industrial plcs functional block dia gram gnd p v ib /v ob v ia /v oa v dd1 gnd p gnd p nc pdis v ddp gnd p v dd2 gnd iso gnd iso gnd iso gnd iso v oa /v ia v ob /v ib nc v sel v iso 1.25v 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 19 20 18 17 1 1 osc rect reg pcs 2-channel i coupler core adum5210/adum5211/ adum5212 10980-001 figure 1 . adum5210 / adum5211 / adum5212 general description the adum5210 / adum5211 / adum5212 1 are dual - channel digital isolators with iso power?, an integrated, isolated dc - to - dc converter . based on the an alog devices, inc., i coupler? technology , t he dc - to - dc converter pro vides regulated, isolated power that is adjustable between 3.15 v and 5.25 v. input supply voltages can range from slightly below the required output to significantly higher. popula r volta ge combination s and their associated power levels are shown in table 1 . th e adum5210 / adum5211 / adum5212 eliminate the need for a separate, isolated dc - to - dc converter in low power, isolated designs. the i coupler chip - scale transformer technology is used for isolated logic signals and for the magnetic components of the dc - to - dc converter. the result is a small form factor, total isolation solution. iso power uses high frequency switching elements to tr ansfer power through its transformer. ta ke s pecial care during printed circuit board (pcb) layout to meet emissions standards. see the an - 0971 application note for board layout recommendations. table 1 . power levels input voltage (v) output voltage (v) output power (mw) 5 5 150 5 3.3 100 3.3 3.3 66 1 protected by u.s. patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. other patents are pending.
adum5210/adum5211/adum5212 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v primary input supply/ 5 v secondary isolated supply ................................................... 3 electrical characteristics 3.3 v primary input supply/ 3.3 v secondary isolated supply ................................................ 5 electrical characteristics 5 v primary input supply/ 3.3 v secondary isolated supply ................................................ 7 package characteristics ............................................................... 9 regulatory approvals ................................................................... 9 insulation and safety - related specifications ............................ 9 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics ............................................................................ 10 recommended operating conditions .................................... 10 absolute maximum ratings ......................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 tr ut h tabl e .................................................................................. 15 typical performance characteristics ........................................... 16 applications information .............................................................. 19 pcb layout ................................................................................. 19 thermal analysis ....................................................................... 20 propagation delay parameters ................................................. 20 emi considerations ................................................................... 20 dc correctness and magnetic field immunity ........................... 20 power consumption .................................................................. 21 insulation lifetime ..................................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 1/ 13 revision 0: initial version
data sheet adum5210/adum5211/adum5212 rev. 0 | page 3 of 24 specifications electrical character istics 5 v primary input su pply/5 v secondary i solated supply all typical specification s are at t a = 25c, v dd1 = v dd2 = v ddp = 5 v, v sel resis tor network : r1 = 10 k , r2 = 30.9 k between v iso and gnd iso . minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 v v dd1 , v dd2 , v ddp 5.5 v and ? 40c t a + 105c, unless otherwise noted. switching specificat ions are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 2 . dc -to - dc converter static specifications parameter symbol min typ max unit test conditions /comments dc - to - dc converter supply setpoint v iso 5.0 v i iso = 15 ma , r1 = 10 k , r2 = 30 .9 k thermal coefficient v iso (tc) ? 44 v/c line regulation v iso (line) 20 mv/v i iso = 15 ma, v ddp = 4.5 v to 5.5 v load regulation v iso (load) 1.3 3 % i iso = 3 ma to 27 ma output ripple v iso (rip) 75 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 27 ma output noise v iso (noise) 200 mv p - p c bo = 0.1 f||10 f, i iso = 27 ma switching frequency f osc 125 mhz pulse - width modulation frequency f pwm 600 khz output supply i iso (max) 30 ma 5.5 v > v iso > 4.5 v efficienc y at i iso (max) 29 % i iso = 27 ma i ddp , no v iso load i ddp (q) 6.8 12 ma i ddp , full v iso load i ddp (max) 30 ma thermal shutdown shutdown temperature 154 c thermal hysteresis 10 c table 3. data channel supply current parameter symbol 1 m b ps a, b, c grades 25 m b ps b, c grades 1 0 0 m b ps c grade unit test conditions / comments min typ max min typ max min typ max supply current adum5210 i dd1 1.1 1. 6 6.2 7.0 20 25 ma c l = 0 pf i dd2 2.7 4.5 4.8 7.0 9.5 15 ma c l = 0 pf adum5211 i dd1 2.1 2. 7 4.9 6. 5 15 19 ma c l = 0 pf i dd2 2.3 2.9 4.7 6. 5 15.6 19 ma c l = 0 pf adum5212 i dd1 2.7 4.5 4.8 7.0 9.5 15 ma c l = 0 pf i dd2 1.1 1.6 6.2 7.0 20 25 ma c l = 0 pf table 4 . switching specifications parameter symbol a grade b grade c grade unit test conditions / comments min typ max min typ max min typ max switching specifications data rate 1 25 1 0 0 mbps within pwd limit propagation delay t phl , t plh 50 35 13 18 24 ns 50% input to 50% output pulse width distortion pwd 1 0 3 2 ns |t plh ? t phl | pulse width pw 1000 40 10 ns within pwd limit propagation delay skew t psk 38 1 2 9 ns between any two units channel matching codirectional t pskcd 5 3 2 ns opposing direction t pskod 10 6 5 ns jitter 2 2 1 ns
adum5210/adum5211/adum5212 data sheet rev. 0 | page 4 of 24 table 5 . input and output characteristics parameter symbol min typ max unit test conditions /comments dc specifications logic high input threshold v ih 0.7 v iso , 0.7 v dd1 v logic low input threshold v il 0.3 v iso , 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0. 1 , v dd2 ? 0. 1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0. 4 , v dd2 ? 0. 4 v dd1 ? 0.2 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0. 2 0.4 v i ox = 4 ma, v ix = v ixl undervolt age lockout v dd1 , v dd2 ,v ddp s upply positive going threshold v uv+ 2. 6 v negative going threshold v uv? 2.4 v hysteresis v uvh 0. 2 v supply current per channel quiescent input supply current i ddi(q) 0.54 0.8 ma quiescent output su pply current i ddo(q) 1.6 2.0 ma dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.04 ma/mbps input currents per channel i i ? 10 +0.01 +10 a 0 v v ix v ddx ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate t r 1.6 s 1 |cm| is the maxim um common - mode voltage slew rate that can be sustained while maintaining v o x > 0.8 v dd1 or 0.8 v iso for a high input or v o x < 0.8 v dd1 or 0 .8 v iso for a low input. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 5 of 24 electrical character istics 3.3 v primary input supply /3.3 v secondary iso lated supply all typical specificatio ns are at t a = 25c, v dd1 =v dd2 = v ddp = 3.3 v, v sel resistor network : r1 = 10 k , r2 = 16. 9 k between v iso and gnd iso . minimum/maximum specifications apply over the entire recommended operation range, which is 3.0 v v dd1 , v dd2 , v ddp 3.6 v, a n d ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. the digital isolator channels and the power section work independently, and under the operating voltages in this section, the re may not be sufficient current from the v iso to run both data channel s at the maximum data rate. verify that the application is within the power capability of v iso if that supply is providing power to v dd2 . table 6 . dc -to - dc converter static specifications parameter symbol min typ max unit test condi tions /comments dc - to - dc converter supply setpoint v iso 3.3 v i iso = 10 ma, r1 = 10 k , r2 = 16. 9 k thermal coefficient v iso (tc) ? 26 v/c i iso = 20 ma line regulation v iso (line) 20 mv/v i iso = 1 0 ma, v dd p = 3.0 v to 3.6 v load regulat ion v iso (load) 1.3 3 % i iso = 2 ma to 18 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 18 ma output noise v iso (noise) 130 mv p -p c bo = 0.1 f||10 f, i iso = 18 ma switching frequency f osc 125 mhz pulse - wi dth modulation frequency f pwm 600 khz output supply i iso (max) 20 ma 3.6 v > v iso > 3 v efficiency at i iso (max) 27 % i iso = 18 ma i ddp , no v iso load i ddp (q) 3.3 10.5 ma i ddp , full v iso load i ddp (max) 77 ma thermal shutdown shu tdown temperature 154 c thermal hysteresis 10 c table 7 . data channel supply current parameter symbol 1 m b ps a, b, c grades 25 m b ps b, c grades 1 0 0 m b ps c grade unit test conditions / comments min typ max min typ max min typ max supply current adum5210 i dd1 0.75 1.4 5.1 9.0 17 23 ma c l = 0 pf i dd2 2.0 3.5 2.7 4.6 4.8 9 ma c l = 0 pf adum5211 i dd1 1.6 2.1 3.8 5.0 11 15 ma c l = 0 pf i dd2 1.7 2.3 3.9 6.2 11 15 ma c l = 0 pf adum5212 i dd1 2.0 3.5 2.7 4.6 4.8 9 ma c l = 0 pf i dd2 0.75 1.4 5.1 9.0 17 23 ma c l = 0 pf table 8 . switching specifications parameter symbol a grade b grade c grade unit test conditions /comments min typ max min typ max min typ max switching specifications data rat e 1 25 1 0 0 mbps within pwd limit propagation delay t phl , t plh 50 35 20 25 33 ns 50% input to 50% output pulse width distortion pwd 1 0 3 2 .5 ns |t plh ? t phl | pulse width pw 1000 40 10 ns within pwd limit propagation delay skew t psk 38 16 12 ns between any two units channel matching codirectional t pskcd 5 3 2 .5 ns opposing direction t pskod 1 0 6 5 ns jitter 2 2 1 ns
adum5210/adum5211/adum5212 data sheet rev. 0 | page 6 of 24 table 9 . input and output characteristics parameter symbol min typ max unit test conditions /comments dc specificatio ns logic high input threshold v ih 0.7 v iso , 0.7 v dd1 v logic low input threshold v il 0.3 v iso , 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0. 1 , v dd2 ? 0. 1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0. 4 , v dd2 ? 0. 4 v dd1 ? 0.2 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervolt age lockout v dd1 , v dd2 ,v ddp s upply positive going threshold v uv+ 2.6 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.2 v supply current per channel quiescent input supply current i ddi(q) 0.4 0.6 ma quiescent output sup ply current i ddo(q) 1.2 1.7 ma dynamic input supply current i ddi(d) 0.08 ma/mbps dynamic output supply current i ddo(d) 0.015 ma/mbps input currents per channel i i ? 10 +0.01 +10 a 0 v v ix v ddx ac specifications output rise/fall time t r /t f 3 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate t r 1.6 s 1 |cm| is the maxim um common - mode voltage slew rate that can be sustained while maintaining v o x > 0.8 v dd1 or 0.8 v iso for a high input or v o x < 0.8 v dd1 or 0.8 v iso for a low input. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 7 of 24 electrical character istics 5 v primary input supply /3.3 v secondary iso lated supply al l typical specifications are at t a = 25c, v dd1 = v ddp = 5 v, v dd2 = 3.3 v , v sel resistor network : r1 = 10 k , r2 = 16. 9 k between v iso and gnd iso . minimum /maximum specifications apply over the entire recommended operation range which is 4.5 v v dd1 , v ddp 5.5 v, 3.0 v v dd2 3.6 v, a n d ? 40c t a + 105c, unless otherwise noted. switching specifications a re tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 10 . dc -to - dc converter static specifications parameter symbol min typ max unit test conditions /comments dc - to - dc converter supply setpoint v iso 3.3 v i iso = 15 ma, r1 = 10 k , r2 = 16. 9 k thermal coefficient v iso (tc) ? 26 v/c line regulation v iso (line) 20 mv/v i iso = 15 ma, v dd p = 4 . 5 v to 5 . 5 v load regulation v iso (load) 1.3 3 % i iso = 3 ma to 27 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 27 ma output noise v iso (noise) 130 mv p -p c bo = 0.1 f||10 f, i iso = 27 ma switching frequency f osc 125 mhz p ulse width modulation frequency f pwm 600 khz output supply i iso (max) 30 ma 3.6 v > v iso > 3 v efficiency at i iso (max) 24 % i iso = 27 ma i ddp , no v iso load i ddp (q) 3.2 8 ma i ddp , full v iso load i ddp (max) 85 ma thermal shutdown shutdown temperature 154 c thermal hysteresis 10 c table 11 . data channel su pply current parameter symbol 1 mbps a, b, c grades 25 mbps b, c grades 1 00 mbps c grade unit test conditions / comments min typ max min typ max min typ max supply current adum5210 i dd1 1.1 1.6 6.2 7.0 20 25 ma c l = 0 pf i dd2 2.0 3.5 2.7 4.6 4.8 9.0 ma c l = 0 pf adum5211 i dd1 2.1 2. 7 4.9 6 .5 15 19 ma c l = 0 pf i dd2 1.7 2.3 3.9 6.2 11 15 ma c l = 0 pf adum5212 i dd1 2.0 3.5 2.7 4.6 4.8 9.0 ma c l = 0 pf i dd2 1.1 1.6 6.2 7.0 20 25 ma c l = 0 pf table 12 . switching specifications 7 codirectional channel matching is the absolute value of the difference in pro pagation delays between any two channels with inputs on the same side of the isolation barrier. opposing - directional channel matching is the absolute value of the difference in propagation delays between any two channels with inpu ts on opposing sides of th e isolation barrier. parameter symbol a grade b grade c grade unit test conditions / comments min typ max min typ max min typ max switching specifications data rate 1 25 1 00 mbps within pwd limit propagation delay t phl , t plh 50 35 13 20 26 ns 50% input to 50% output pulse width distortion pwd 1 0 3 2 .5 ns |t plh ? t phl | pulse width pw 1000 40 10 ns within pwd limit propagation delay skew t psk 38 16 1 2 ns between any two units channel matching codirectional t pskcd 5 3 2 ns opposing direction t pskod 1 0 6 5 ns jitter 2 2 1 ns
adum5210/adum5211/adum5212 data sheet rev. 0 | page 8 of 24 table 13 . input and output characteristics parameter symbol min typ max unit test conditions /comments dc specifications logic high input threshold v ih 0.7 v iso , 0.7 v dd1 v logic low input threshold v il 0.3 v iso , 0.3 v dd1 v logic high output voltages v oh v dd1 ? 0. 1 , v dd2 ? 0. 1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0. 4 , v dd2 ? 0. 4 v dd1 ? 0.2 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl undervolt age lockout v dd1 , v dd2 ,v ddp s upply positive going threshold v uv+ 2.6 v negative going threshold v uv? 2.4 v hysteresis v uvh 0.2 v supply current per channel quiescent input supply current i ddi(q) 0.54 0.75 ma quiescent output s upply current i ddo(q) 1.2 2.0 ma dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.02 ma/mbps input currents per channel i i ? 10 +0.01 +10 a 0 v v ix v ddx ac specifications output rise/fall tim e t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 25 35 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v refresh rate t r 1.6 s 1 |cm| is the maxim um common - mode voltage slew rate that can be sustained while maintaining v o x > 0.8 v dd1 or 0.8 v iso for a high input or v o x < 0.8 v dd1 or 0.8 v iso for a low input. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 9 of 24 package characterist ics table 14 . thermal and isolation char acteristics parameter symbol min typ max unit test conditions /comments resistance (input to output) 1 r i- o 10 12 capacitance (input to output) 1 c i- o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - ambient thermal resistance ja 50 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 3 1 the device is considered a 2 - terminal device: pin 1 t hrough pin 10 are s horted together , and pin 11 t hrough pin 20 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the thermal analysis section for thermal model definitions. regulatory approvals table 15. ul (pending) 1 csa (pending) vde (pending) 2 recognized under 1577 component reco g nition program 1 approved under csa co mponent acceptance notice #5a certified according to din v vde v 0884 -10 (vde v 0884 - 10):2006-12 2 single protection , 2500 v rms isolation voltage basic insulation per csa 60950-1-03 and iec 60950 - 1, 400 v rms (565 v peak) maximum working vol t age reinfor ced insulation, 56 0 v peak file e214100 file 205078 file 2471900 -4880-0001 1 in accordance with ul 1577, each adum5210 / adum5211 / adum5212 is proof tested by applying an insulation test voltage 3 000 v rms for 1 second (current leakage det ection limit = 10 a). 2 in accordance with din v vde v 0884 - 10, each adum5210 / adum5211 / adum5212 is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884 - 1 0 approval. insulation and safet y - related specificatio ns table 16 . critical safety - related dimensions and material properties parameter symbol value unit test condit ions/comments rated dielectric insulation voltage 2500 v rms 1- minute duration minimum external air gap (clearance) l(i01) 5.3 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i0 2) 5.3 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm distance through insulation tracking resistance (comparative tracking index ) cti >400 v din iec 112/vd e 0303, part 1 isolation group ii material group (din vde 0110, 1/89, table 1)
adum5210/adum5211/adum5212 data sheet rev. 0 | page 10 of 24 din v vde v 0884 - 10 (vde v 0884- 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. mainten ance of the safety data is ensured by the protective circuits. the asterisk (*) marking on packages denotes din v vde v 0884 - 10 approval. table 17 . vde characteristics description test conditions /comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulati on voltage v iorm 560 v peak input -to - output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec , partial discharge < 5 pc v pd(m) 1050 v peak input -to - output test voltage, method a after environmental tests subgr oup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 840 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 672 v peak hig hest allowable overvoltage v iotm 3535 v peak surge isolation voltage v iosm(test) = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 4000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2) case temperature t s 150 c safety total dissipated power i s1 2.5 w insulation resistance at t s v io = 500 v r s >10 9 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200 ambient temperature (c) safe limiting power (w) 10980-002 figure 2 . thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884 - 10 recommended operatin g conditions table 18. parameter symbol min max unit operati ng temperature 1 t a ? 40 +105 c supply voltages 2 v ddp at v iso = 3.0 v to 3.6 v v ddp 3.0 5.5 v v ddp at v iso = 4.5 v to 5.5 v 4.5 5.5 v v dd1 , v dd2 v dd1 , v dd2 2.7 5.5 v 1 operation at 105c requires reduction of the maxi mum load current as specified in table 19. 2 each voltage is relative to its respective ground.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 11 of 24 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted . table 19. parameter rating storage temperature (t st ) ? 55c to +150c ambient operating temperature (t a ) ? 40c to +105c supply voltages (v ddp , v dd1 , v dd2 , v iso ) 1 ? 0.5 v to +7.0 v v iso supply current 2 t a = ?40c to +105c 30 ma input voltage (v ia , v ib , pdis, v sel ) 1 , 3 ? 0.5 v to v ddi + 0.5 v output voltage ( v oa , v ob ) 1 , 3 ? 0.5 v to v ddo + 0.5 v average output current per data out put pin 4 ? 10 ma to +10 ma common - mode transients 5 ? 100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 t he v iso provides current for dc and dynamic loads on the v iso i/o channels. this current must be included when determining the total v iso supply current. for ambient temperatures between 85c and 105c , maximum allowed curren t is reduced. 3 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 4 see figure 2 for the maximum rated current values for various temperatures . 5 refers to common - mode transients across the insulation barrier. common - mode transients exceeding th e absolute maximum ratings may cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 20. maximum continu ous working volt age supporting 50 - year minimum lifetime 1 parameter max unit applicable certification ac voltage bipolar waveform 560 v peak all certifications, 50- year operation unipolar waveform 560 v peak dc voltage |dc peak voltage | 56 0 v peak 1 refers to the continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime sect ion for more information. esd caution
adum5210/adum5211/adum5212 data sheet rev. 0 | page 12 of 24 pin configuration s and function descrip tions 1 2 3 4 20 19 18 17 5 16 6 15 7 14 8 9 10 13 12 11 adum5210 top view (not to scale) gnd p v ib v ia v dd1 gnd p gnd p nc pdis v ddp gnd p v dd2 notes 1. pins labeled nc can be allowed to float, but it is better to connect these pins to ground. avoid routing high speed signals through these pins because noise coupling may result. gnd iso gnd iso gnd iso gnd iso v oa v ob nc v sel v iso 10980-003 figure 3 . adum5210 pin configuration table 21. adum5210 pin function descriptions pin no. mnemonic description 1 v dd1 powe r supply for the side 1 logic circuits of the device . it is independent of v ddp and can operate between 3.0 v and 5.5 v. 2, 5, 6, 10 gnd p ground reference for isolator side 1. all of these pins are internally connected, and it is recommended that all gnd p pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 7 , 14 nc this pin is not connected internally (see figure 3 ). 8 pdis power disable. when this pin is tied to a logic low , the power converter is active ; when tied to a logic high , the power supply enters a low power standby mode. 9 v ddp primary iso power supply voltage, 3.0 v to 5.5 v . 11, 15, 16, 19 gnd iso ground reference for isolator side 2. all of these pins are internally connected, and it is recommended that all gnd iso pins be connected to a common ground. 12 v iso secondary supply voltage output for external loads, 3.3 v (v sel low ) or 5.0 v (v sel high ). 13 v sel output voltage se lect . provide a thermally matched resistor network between v iso and gnd iso to divide the required output voltage to match the 1.25 v reference voltage. v iso voltage can be programmed up to 20% higher or 75% lower than v ddp but must be within the allowed output voltage range. 17 v ob logic output b . 18 v oa logic outpu t a. 20 v dd2 power supply for the side 2 logic circuits of the device . it is independent of v iso and can operate between 3.0 v and 5.5 v.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 13 of 24 1 2 3 4 20 19 18 17 5 16 6 15 7 14 8 9 10 13 12 11 adum5211 top view (not to scale) gnd p v ib v oa v dd1 gnd p gnd p nc pdis v ddp gnd p v dd2 gnd iso gnd iso gnd iso gnd iso v ia v ob nc v sel v iso 10980-005 notes 1. pins labeled nc can be allowed to float, but it is better to connect these pins to ground. avoid routing high speed signals through these pins because noise coupling may result. figure 4 . adum5211 pin configuration ta ble 22. adum5211 pin function descriptions pin no. mnemonic description 1 v dd1 power supply for the side 1 logic circuits of the device . it is independent of v ddp and can operate betw een 3.0 v and 5.5 v. 2, 5, 6, 10 gnd p ground reference for isolator side 1. all of these pins are internally connected, and it is recommended that all gnd p pins be connected to a common ground. 3 v oa logic output a. 4 v ib logic input b. 7, 14 nc this p in is not connected internally (see figure 4). 8 pdis power disable. when this pin is tied to a logic low, the power converter is active; when tied to a logic high, the power supply enters a low power standby mode. 9 v ddp primar y iso power supply voltage, 3.0 v to 5.5 v . 11, 15, 16,19 gnd iso ground reference for isolator side 2. all of these pins are internally connected, and it is recommended that all gnd iso pins be connected to a common ground. 12 v iso secondary supply voltage output for external loads, 3.3 v (v sel low ) or 5.0 v (v sel high ). 13 v sel output voltage se lect . provide a thermally matched resistor network between v iso and gnd iso to divide the required output voltage to match the 1.25 v reference voltage. v iso voltag e can be programmed up to 20% higher or 75% lower than v ddp but must be within the allowed output voltage range. 17 v ob logic output b. 18 v ia logic input a. 20 v dd2 power supply for the side 2 logic circuits of the device. it is independent of v iso and can operate between 3.0 v and 5.5 v.
adum5210/adum5211/adum5212 data sheet rev. 0 | page 14 of 24 1 2 3 4 20 19 18 17 5 16 6 15 7 14 8 9 10 13 12 11 adum5212 top view (not to scale) gnd p v ob v oa v dd1 gnd p gnd p nc pdis v ddp gnd p v dd2 gnd iso gnd iso gnd iso gnd iso v ia v ib nc v sel v iso 10980-007 notes 1. pins labeled nc can be allowed to float or can be connected to the ground. avoid connecting them to high speed signals to minimize capacitive coupling of noise. figure 5 . adum5212 pin configuration table 23. adum5212 pin function descriptions pin no. mnemonic description 1 v dd1 power supply for the side 1 logic circuits of the device . it is independent of v ddp and can operate between 3.0 v and 5.5 v. 2, 5, 6, 10 gnd p ground reference for isolator side 1. all of these pins are in ternally connected, and it is recommended that all gnd p pins be connected to a common ground. 3 v oa logic output a. 4 v ob logic output b. 7, 14 n c this pin is not connected internally (see figure 5). 8 pdis power disable . when this pin is tied to a logic low , the power converter is active; when tied to a logic high , the power supply enters a low power standby mode. 9 v ddp primary iso power supply voltage, 3.0 v to 5.5 v . 11, 15, 16, 19 gnd iso ground reference for isolator side 2. all of these pins are internally connected, and it is recommended that all gnd iso pins be connected to a common ground. 12 v iso secondary supply voltage output for external loads, 3.3 v (v sel low ) or 5.0 v (v sel high ). 13 v sel output voltage se lect . provide a thermally matched resistor network between v iso and gnd iso to divide the required output voltage to match the 1.25 v reference voltage. v iso voltage can be programmed up to 20% higher or 75% lower than v ddp but must be within the allowed output v oltage range. 17 v ib logic input b . 18 v ia logic input a. 20 v dd2 power supply for the side 2 logic c ircuits of the device. it is independent of v iso and can operate between 3.0 v and 5.5 v.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 15 of 24 truth table table 24. power sectio n truth table (positive logic) v ddp (v) v sel input pdis input v iso output (v) notes 5 r1 = 10 k, r2 = 30.9 k, low 5 5 r1 = 10 k, r2 = 30.9 k, high 0 3.3 r1 = 10 k, r2 = 16.9 k low 3.3 3.3 r1 = 10 k, r2 = 16.9 k high 0 5 r1 = 10 k, r2 = 30.9 k, low 3.3 5 r1 = 10 k, r2 = 30.9 k, high 0 3.3 r1 = 10 k, r2 = 16.9 k low 5 configuration not recommended 3.3 r1 = 10 k, r2 = 16.9 k high 0 table 25. data section truth table (positive logic) v ddi state 1 v ix input 1 v ddo state 1 v ox output 1 notes powered high powered h igh normal operation, data is high powered l ow powered l ow normal operation, data is low x 2 x 2 unpowered z 3 output is off unpowered l ow powered l ow output default low unpowered h igh powered indeterminate if a high level is applied to an input when no supply is present, then it can parasitically power the input side causing unpredictable operation 1 the references to i and o in this table refer to the input side and output side of a given data pa th and the associated power supply . 2 x = dont care. 3 z = h igh i mpedance state .
adum5210/adum5211/adum5212 data sheet rev. 0 | page 16 of 24 typica l performance charac teristics 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 0.02 0.04 0.06 0.08 load current (a) efficiency (%) 10980-004 v dd1 = v ddp = 5v/v dd2 = 5v v dd1 = v ddp = 5v/v dd2 = 3.3v v dd1 = v ddp = 3.3v/v dd2 = 3.3v figure 6 . typical power supply efficiency at 5 v/5 v, 5 v/3.3 v, and 3.3 v/3.3 v 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 0 1 0 2 0 3 0 4 0 p o w e r d i ss i p a t i o n ( m w ) i i s o ( m a ) 10980-006 v dd1 = v ddp = 5v/v dd2 = 3.3v v dd1 = v ddp = 3.3v/v dd2 = 3.3v v dd1 = v ddp = 5v/v dd2 = 5v figure 7 . typical total power dissipation vs. i iso 10980-008 0 5 1 0 1 5 2 0 2 5 3 0 3 5 0 2 5 5 0 7 5 1 0 0 i i s o ( m a ) i d d p ( m a ) v dd1 = v ddp = 5v/v dd2 = 3.3v v dd1 = v ddp = 3.3v/v dd2 = 3.3v v dd1 = v ddp = 5v/v dd2 = 5v figure 8 . typical isolated output supply current, i iso , as a function of external load, at 5 v/5 v, 5 v/3.3 v, and 3.3 v/3.3 v 0 0.4 0.2 0.8 0.6 1.0 1.4 1.8 1.6 2.0 0 0.10 0.05 0.20 0.15 0.25 0.30 0.40 0.45 0.35 0.50 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd1 (v) power dissipation (w) i ddp current (a) 10980-009 power dissipation i ddp figure 9 . typical short - circuit input current and power vs. v dd1 supply voltage (1ms/div) v iso (100mv/div) 10% load 90% load 10980-010 figure 10 . typical v iso transient load response, 5 v output, 10% to 90% load step (1ms/div) v iso (100mv/div) 10% load 90% load 10980-0 1 1 figure 11 . typical transient load response, 3 v output, 10% to 90% load step
data sheet adum5210/adum5211/adum5212 rev. 0 | page 17 of 24 (1ms/div) v iso (100mv/div) 10980-013 figure 12 . typical transient loa d response, 5 v input , 3 .3 v output, 10% to 90% load step v iso (v) time ( s) 4.970 4.965 4.960 4.955 4.950 4.945 4.940 1 0 2 3 4 10980-014 figure 13 . typical v iso = 5 v output voltage ripple at 90% load v iso (v) time ( s) 3.280 2.278 3.276 3.274 3.272 3.270 1 0 2 3 4 10980-015 figure 14 . typical v iso = 3.3 v output voltage ripple at 90% load 2.0 2.5 3.0 3.5 4.0 4.5 5.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 minimum input vo lt age (v) output vo lt age (v) 3 0 m a loa d 2 0 m a loa d 1 0 m a loa d 10980- 1 15 figur e 15 . relationship between output voltage and required input voltage, under load, to maintain >80% duty factor in the pwm 500 450 400 350 300 250 200 150 100 ?20 0 20 40 ambient temper a ture (c) power dissi pa tion (mw) 60 80 100 120 ?40 v dd1 = v ddp = 5v/v dd2 = 5v v dd1 = v ddp = 5v/v dd2 = 3.3v 10980- 1 16 figure 16 . power dissipation with a 30 ma load vs. temperature 500 450 400 350 300 250 200 150 100 ?20 0 20 40 ambient temper a ture (c) power dissi pa tion (mw) 60 80 100 120 ?40 v ddp = 5v/v dd2 3.3v v dd1 = 3.3v/v dd2 = 3.3v v dd1 = 5v/v dd2 = 5v 10980- 1 17 figure 17 . power dissipation with a 20 ma load vs. temperature
adum5210/adum5211/adum5212 data sheet rev. 0 | page 18 of 24 1 0 0 2 4 6 8 0 2 0 4 0 6 0 8 0 10 0 1 0 3 0 5 0 7 0 9 0 da t a ra t e (m bp s ) 5 v 3 .3v 10980-016 supply curr e n t ( m a ) figure 18 . typical supply current per input channel vs. data rate for 5 v and 3 .3 v operation 1 0 0 2 4 6 8 0 2 0 4 0 6 0 8 0 10 0 1 0 3 0 5 0 7 0 9 0 da t a ra t e (m bp s ) 5 v 3 .3v 10980-017 supply curr e n t ( m a ) figure 19 . typical supply cu rrent per output channel vs. data rate for 5 v and 3 .3 v operation (no output load) 1 0 0 4 2 6 8 0 2 0 4 0 6 0 8 0 100 1 0 3 0 5 0 7 0 9 0 da t a ra t e (m bp s ) 5 v 3 .3v 10980-018 supply curr e n t ( m a ) figure 20 . typical supply current per output channel vs. data rate for 5 v and 3 .3 v operation (15 pf output load) 2 0 0 5 1 0 1 5 0 2 0 4 0 6 0 8 0 10 0 1 0 3 0 5 0 7 0 9 0 da t a ra t e (m bp s ) 5 v 3 v 10980-019 supply curr e n t ( m a ) figure 21 . typical adum5210 v dd1 or adum5212 v dd2 supply current vs. data rate for 5 v and 3 .3 v operation 2 0 0 5 1 0 1 5 0 2 0 4 0 6 0 8 0 100 1 0 3 0 5 0 7 0 9 0 supply curr e n t ( m a ) da t a ra t e (m bp s ) 5 v 3 .3v 10980-020 figure 22 . typical adum5210 v dd2 or adum5212 v dd2 supply current vs. data rate for 5 v and 3 .3 v operation 2 0 0 5 1 0 1 5 0 2 0 4 0 6 0 8 0 10 0 1 0 3 0 5 0 7 0 9 0 supply curr e n t ( m a ) da t a ra t e (m bp s ) 5 v 3 .3v 10980-012 figure 23 . typical adum5211 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 .3 v operation
data sheet adum5210/adum5211/adum5212 rev. 0 | page 19 of 24 applications information the dc - to - dc converter section of the adum5210 / adum5211 / adum5212 works on principles that are common to most modern power supplies. it ha s a s plit controller architecture with isolated pulse - width modulation (pwm) feed back. v ddp power i s supplied to an oscillating circuit that switches current into a chip - scale air core transformer. power transferred to the secondary side is rectified and regulated to a value between 3.15 v and 5.25 v , depending on the setpoint supplied by an external vo ltage divider ( s ee equation 1 ) . the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v dd p ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. r1 r2 r1 v iso ) ( v 25 . 1 + = (1) w here: r1 is a resistor between v sel and gnd iso . r2 is a resistor between v sel and v iso . because the output voltage can be a djusted continuously there are an infinite number of operating conditions. this data sheet addresses three discrete operating conditions in the specifications tables. many other combinations of input and output voltage are possi ble; figur e 15 depicts the supported voltage combinations at room temperature. figur e 15 was generated by fixing the v iso load and decreasing the input voltage until the pw m was at 80% duty cycle. each of the curves represents the minimum input voltage that is required for operation under this criterion. for example, if the applica - tion requires 30 ma of output current at 5 v, the minimum input voltage at v ddp is 4.25 v. figur e 15 also illustrates why the v ddp = 3.3 v input and v iso = 5 v configuration is not recommended. even at 10 ma of output current, the pwm cannot maintain less than 80% duty factor, leaving no margin to support load or temperature variations. typically, the adum5210 / adum5211 / adum5212 dissipate about 17% more power betwe en room temperature and maxi - mum temperature; therefore, the 20% pwm margin covers temperature variations. the adum5210 / adum5211 / adum5212 implement undervoltage lockout (uvlo) with hysteresis on the primary and secondary side i/o pins as well as the v ddp power input . this feature ensures that the converter does not go into oscillation due to noisy input power or slo w power - on ramp rates. pcb layout the adum5210 / adum5211 / adum5212 digital isolators with 0. 1 5 w iso power integrat ed dc - to - dc converters require no exter - nal interface circuitry for the logic in terfaces. power supply bypass ing with a low esr capacitor is required , as close to the chip pads as possible . the iso power inputs require several passive components to bypass the power effectively as well as set the output voltage and bypass the core voltage regulator (see figure 24 through fig ure 26) . pdis v ddp gnd p 10 f 0.1 f + 8 9 10 10980-022 figure 24 . v ddp bias and bypass components v sel v iso gnd iso 10 f 0.1 f + r1 10k ? r2 30k ? 13 12 11 10980-023 f igure 25 . v iso bias and bypass components the power supply section of the adum5210 / adum5211 / adum5212 uses a 125 mhz oscillator frequency to efficiently pass power through its chip - scale transformers . bypass capaci - tors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor ; ripp le suppression and proper regulation require a large value bulk capacitor. these capacitors are most conveniently connecte d between pin 9 and pin 10 for v ddp and between pin 11 and pin 12 for v iso . to suppress noise and reduce ripple, a parallel combinatio n of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 . the smaller capacitor must have a low esr; for example, use of an npo or x5r ceramic capacitor i s advised. ceramic capacitors are also recommended for the 10 f bulk capacitance . an additional 10 nf capac itor can be added in parallel if further emi reduction is required. note that the total lead length between the ends of the low esr capacitor and the input pow er supply pin must not exceed 2 mm. gnd iso v se l pdis v dd p v iso gnd p by p ass < 2mm gnd iso adum5210/ adum5211/ adum5212 10980-024 gnd p v ib /v ob v ia /v oa v ob /v ib v oa /v ia v dd1 v dd2 gnd p gnd iso fig ure 26 . recommended pcb layout in applications involving high common - mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occu r equally affects all pins on a given component side.
adum5210/adum5211/adum5212 data sheet rev. 0 | page 20 of 24 failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in table 19, thereby leading to latch - up and/or permanen t damage. thermal analysis the adum5210 / adum5211 / adum5212 consist of four internal die attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis, the chip is treated as a thermal unit, with the highest junction temperature reflected in t he ja from table 14 . the value of ja is based on measurements taken with the parts mounted on a jedec standard, 4 - layer board with fine width traces and still air. under normal operating conditions, the adum5210 / adum5211 / adum5212 can operate at full load across the full temperature range without derating the output current . propagation delay parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 27 ). the propagation delay to a logic low output may dif fer from the propagation delay to a logic high. i n p u t (v i x ) o u t p u t (v o x ) t p l h t p h l 50 % 50 % 10980-025 figure 27 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel - to - channel matching refers to the maximum amount the propagation delay differs between channels within a single adum5210 / adu m5211/ adum5212 component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5210 / adum5211 / adum5212 devices operating under the same conditions. emi considerations the dc - to - dc converter section of the adum5210 / adum5211 / adum5212 components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. this creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recom - mended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. see the an - 0971 application note for the most current pcb layout recommendations for the adum5210 / adum5211 / adum5212 . dc correctness and m agnetic field immuni ty positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 .6 s, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than approximately 6.4 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a defaul t low state by the watchdog timer circuit. this situation should occur in the adum5210 / adum5211 / adum5212 only d uring power - up and power - down operations. the limitation on the adum5210 / adum5211 / adum5212 magnetic field immun ity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3.3 v operating condition of the adum5210 / adum5211 / adum5212 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude of >1. 5 v. the decoder has a sensing threshold of about 0.5 v, thus estab - lishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = (? d /dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum5210 / adum5211 / adum5212 and an imposed require ment that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 28. m a g n e t i c f i e l d f r e q u e nc y ( h z) 10 0 m a x i m u m a ll o w ab l e m a g n e t i c fl u x d e n s i t y ( k g a u ss ) 0 . 00 1 1 m 1 0 0 . 0 1 1 k 10 k 10 m 0 . 1 1 100 m 100 k 10980-026 figure 28 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum all owable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and is of the wo rst - case polarity), it reduces the received pulse from >1.0 v to 0.75 v, which is still well above the 0.5 v sensing threshold of the decoder.
data sheet adum5210/adum5211/adum5212 rev. 0 | page 21 of 24 the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum5210 / adum5211 / adum5212 transformers. figure 29 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown in figure 29 , the adum5210 / adum5211 / adum5212 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example, a 0.5 ka current , placed 5 mm awa y from the adum5210 / adum5211 / adum5212 , is required to affect component operation. magnetic field f reque nc y (hz) maximum a ll ow ab le curr ent (ka) 1k 10 0 10 1 0.1 0.01 1k 10 k 100 m 100 k 1m 10 m dist anc e = 5m m dist anc e = 1m dist anc e = 100m m 10980-027 figure 29 . maximum allowable current for various current - to - adum521x spacings note that, in combinations of strong magnetic field and high frequency, any loops formed by pcb traces can induce error voltages sufficiently large to trigger the thresholds of suc ceeding circuitry. exercise care in the layout of such traces to avoid this possibility. power consumption the v dd p power supply input provides power only to the converter. power for the data channels is provided through v dd1 and v dd2 . these power supplies can be connected to v ddp and v iso , if desired , or the supplies can receive power from an independent source. the converter should be treated as a standalone supply to be utilized at the discretion of the designer. the v dd1 or v dd2 supply current at a give n channel of the adum5210 / adum5211 / adum5212 isolator is a function of the supply voltage, the data rate of the c hannel, and the output load of the channel. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi(d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo q ) f > 0.5 f r where: i ddi(d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). i ddi(q) , i ddo(q) are the specified input and output quiescent supply currents (ma) . f is the input logic signal frequency (mhz); it is half the input data rate, expressed in units of mbps. f r is the input stage refresh rate (mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 18 and figure 19 show per - channel supply currents as a function of data rate for an unloaded output condition. figure 20 shows the per - channel supply current as a function of data rate for a 15 pf output condition. figure 21 through figure 23 show the total v dd1 and v dd2 supply current as a function of data rate for adum5210 / adum5211 / adum5212 channel configurations.
adum5210/adum5211/adum5212 data sheet rev. 0 | page 22 of 24 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. analog devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the adum5210 / adum5211 / adum5212 . accelerated life testing is performed using voltage levels higher than the rated con tinuous working voltage. acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. the values shown in table 20 summarize the peak voltage s for 50 years of service life in several operating conditions. in many cases, the working voltage approved by agency testing is higher than the 50 - year service life voltage. operation at working voltages higher than the service life voltage listed leads t o premature insulation failure. the insulation lifetime of the adum5210 / adum5211 / adum5212 depends on the voltag e waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates, depending on whether the wave - form is bipolar ac, unipolar ac, or dc. figure 30 , figure 31 , and figure 32 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. a 50 - year operating lifetime under the bipolar ac condition determine s the analog devices recommended maximum working voltage. in the case of dc or unipolar ac voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. the wor king voltages listed in table 20 can be applied while maintaining the 50- year minimum lifetime, provided the voltage conforms to either the dc or unipolar ac voltage cases. any cross - insulation voltage waveform that does not confo rm to figure 31 or figure 32 must be treated as a bipolar ac waveform, and its peak voltage must be li mited to the 50 - year lifetime voltage value listed in table 20. 0v rated peak voltage 10980-028 figure 30 . bipolar ac waveform 0v rated peak voltage 10980-029 figure 31 . dc waveform 0v rated peak voltage 10980-030 notes 1. the voltage is shown as sinusoidal for illustration puposes only. it is meant to represent any voltage waveform varying between 0v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0v. figure 32 . unipolar ac waveform
data sheet adum5210/adum5211/adum5212 rev. 0 | page 23 of 24 outline dimensions compliant t o jedec s t andards mo-150-ae 060106- a 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 33 . 20- lead shrink small outline package [ssop] (rs - 20) dimensions shown in millimeters ordering guide model 1 , 2 number of inputs, v ddp side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse wi dth distortion (ns) temperature range ( c) package description package option adum5210 arsz 2 0 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5210 arsz - rl 7 2 0 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5210 brsz 2 0 25 40 3 ? 40 to +105 20 - lead ssop rs - 20 adum5210 brsz - rl 7 2 0 25 40 3 ? 40 to +105 20- lead ssop rs - 20 adum5210 crsz 2 0 100 15 2 ? 40 to +105 20- lead ssop rs - 20 adum5210 crsz - rl 7 2 0 100 15 2 ? 40 to +105 20- lead ssop rs - 20 adum5211 arsz 1 1 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5211 arsz - rl 7 1 1 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5211 brsz 1 1 25 40 3 ? 40 to +105 20- lead ssop rs - 20 adum52 11 brsz - rl 7 1 1 25 40 3 ? 40 to +105 20- lead ssop rs - 20 adum5211 crsz 1 1 100 15 2 ? 40 to +105 20- lead ssop rs - 20 adum5211 crsz - rl 7 1 1 100 15 2 ? 40 to +105 20 - lead ssop rs - 20 adum5212 arsz 0 2 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5212 arsz - rl 7 0 2 1 75 40 ? 40 to +105 20- lead ssop rs - 20 adum5212 brsz 0 2 25 40 3 ? 40 to +105 20- lead ssop rs - 20 adum5212 brsz - rl 7 0 2 25 40 3 ? 40 to +105 20- lead ssop rs - 20 adum5212 crsz 0 2 100 15 2 ? 40 to +105 20- lead ssop rs - 20 adum5212 crsz - rl 7 0 2 100 15 2 ? 40 to +105 20- lead ssop rs - 20 1 the addition of an rl7 suffix designates a 7 tape and reel option. 2 z = rohs compliant part.
adum5210/adum5211/adum5212 data sheet rev. 0 | page 24 of 24 notes ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10980-0-1/13(0)

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